During the design of an application specific integrated circuit (ASIC) or system-on-chip (SOC), design for test (DFT) and automatic test pattern generation (ATPG) methodologies are typically used to develop a test sequence that, when applied to the ASIC or SOC, can detect potential failures of the ASIC or SOC. After the ASIC or SOC has been manufactured, it can be placed into a scan mode, which forces all the flip-flops in the device to be connected in a simplified fashion, and these test sequences can be used to test all the flip-flops, as well as to trace failures to specific flip-flops.
Meanwhile, SOC design using reusable intellectual property (IP) cores has become a state-of-the-art implementation paradigm for IP core providers and system integrators. The IP cores are pre-designed and pre-verified by the core providers. Special test access mechanisms (TAMs) are required to facilitate core-based SOC test. To enable both core reuse and easy test access, the embedded cores are connected to the TAMs using special interfaces called core wrappers. However, wrapping a core using current DFT techniques may present area and timing issues that adversely affect an integrated circuit design.